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Product model: IS200JGNDG1AAA

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GE General Electric Technical Specifications: IS200JGNDG1AAA

An example IS200JGNDG1AAA of how to use the VME-SASI with a SASI

controller for programming purposes is given in this section.

The IS200JGNDG1AAA basic SASI protocol must always be followed, or errors

will occur. The basic SASI protocol is described below, and

an example of a DMA read or write is presented.


brand Product Name Product model Order No
GE Fanuc Module card IS200JGNDG1AAA nothing
Place of Origin Marketable land Imported or not defects liability period
Europe and America Nationwide and overseas yes a year
Place of shipment Delivery method How to use Applicable industries
Xiamen Shunfeng Express Commissioning and installation Power Plant Steel Plant Cement Plant Shipboard Papermaking
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The protocol discussed here is only applicable to the

software and hardware protocol which must be monitored

by the user program while using the VME-SASI. Interface

signals, which provide status of the present condition of the

interface, are available in the IS200JGNDG1AAA DMA status register. The

description of the status bits is given in the register

definition section. Table 6 presents typical interface phases

identified by the state of the status bits.

The DMA STATUS BSY* bit signifies that the controller is

selected and is either awaiting a command or executing a

command. When the BSY* bit returns high, the command

IS200JGNDG1AAA has been completed, including all of the data and status

transfers to and from the controller.

If the controller is in an unknown state, or if execution is

beginning from power up, the controller should be reset. To

reset the controller, set the reset bit of the DMA CONTROL

register highthen low. The STATUS register bits BSY*, I/O,

C/D, and MSG* should be ‘1’ following a reset.

The controller sequence to execute a command is constant.

The sequence is as follows. When reading or writing bytes

to the controller command/status, select, or data registers,

ensure that the REQ* bit in the DMA status register is ‘0’.

REQ* low means the controller either wants data or has

data ready. If the controller registers are accessed before

the controller is ready, a bus timeout will probably occur.

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