Product name:

Product model: IS200TTURH1A

Quantity: inventory

Part No./PN: IS200TTURH1A

Warranty: We provide warranty service for IS200TTURH1A

Shipping Port:FuJian

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GE General Electric Technical Specifications: IS200TTURH1A

Network Target Data (NTD) BAR2 (Offset $18): A 32‐bit register containing the

IS200TTURH1A data associated with one of the four network interrupts that will be sent to the

target (destination) node. Writing data to this register does not initiate the actual

interrupt; only writing to the Network Interrupt Command (NIC) register will do

The NTD register is both read and write accessible.

IS200TTURH1A Network Target Node (NTN) BAR2 (Offset $1C): An 8‐bit register containing the

node ID of the target (destination) node. Writing to the NTN register does not

initiate the actual network interrupt. This register is both read and write

accessible. The NTN register can be written or read with the Network Interrupt

Command Register  as a single 16‐bit word.


brand Product Name Product model Order No
GE Fanuc Module card IS200TTURH1A nothing
Place of Origin Marketable land Imported or not defects liability period
Europe and America Nationwide and overseas yes a year
Place of shipment Delivery method How to use Applicable industries
Xiamen Shunfeng Express Commissioning and installation Power Plant Steel Plant Cement Plant Shipboard Papermaking
Service advantages Foreign import, goods preparation and supply Reasonable price and reliable quality Pictures are for reference only
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IS200TTURH1A Network Interrupt Command (NIC) BAR2 (Offset $1D): An 8‐bit register

containing a four‐bit code that defines the type of network interrupt issued. See

Table 3‐46 on page 56 for a definition of the possible codes. The NIC is both read

and write accessible. Only writing to the NIC register will initiate the network

interrupt. The network interrupt is transmitted in order following after all

IS200TTURH1A previously written data

The NTD, NTN and the NIC registers described above are used to generate

network interrupts. Four pairs of registers described below are involved with

receiving those network interrupts.

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