GE IS200TBAIH1CDC Control system PCB with 2 terminal blocks

Description

GE General Electric Technical Specifications: IS200TBAIH1CDC

The I/O cables which connect to MOX cards installed in the

card cage shciuldbe routed to the right in front of the card

cage through the cable port on the right. The strain relief

bracket on the IS200TBAIH1CDC right is used to secure the flat cables for

distribution to external devices. Sec·ure cables against the

bracket and tighten the two (2) thumbscrews.

MDX Circuit Board Installation

The MOXcircuit boards are installed in the card cage with

components facing to the left (user looking at card cage from

front). The retaining bracket must be removed to install the

Figure 5

IS200TBAIH1CDC cards. Quarter-turn thumb screws are used to install the

retaining bracket. The boards must be installed with the

card ejector up. The MO CC-16 is designed to prevent

backwards installation of the STO BUS boards.

Priority Chain

The card cage is prioritized for interrupts from right to left.

This means the highest priority interrupting device may be

placed in the right-most slot. The lowest priority slot is far

left. For a particular installation requiring both a complete

interrupt· priority daisy chain and an empty slot, wire

wrappable posts are provided on the motherboard for

jumpering the priority chain.

The IS200TBAIH1CDC laO CPU (MK3880-4) features a 158 unit instruction

set, single phase clock input, automatic dynamic memory

refresh and an advanced set of addressing modes. This CPU

generates all of the required addresses and control signals

required for communication and control of data to and from

memories and peripherals. It fetches and executes

instructions and provides most of the timing signals

required for proper operation of the board.

IS200TBAIH1CDC EPROM

The SOlE-COMBO board makes use of Mostek’s

BYTEWYDE memory concept by providing two 28-pin

sockets that accept either 2K by 8 or 8K by 8 ROMs or

EPROMs. When using 2K by 8 memories, each memory

chip is inserted offset into the socket such that pins 1, 2, 27,

and 28 are exposed and therefore not used. The memory

control and addressing circuitry has a feawre which allows

the entire 65K bytes of memory to be addressed directly by

the,user. This is referred to as “Shadow Memory”, In the

SOlE-COMBO board, the term applies to the two EPROM

sockets which may replace a portion of the main 65K of

DRAM after a reset and can be enabled and disabled at will

by any program. This ability of the COMBO to eliminate the

EPROM/ROM socket from the addressing range ofthe Z80

is possible thru software control. Bit 04 of Port E2 controls

this function. Any 2716 or 2764 type EPROM may be used

as long as the access time from JOE is less than 335

nano-seconds.

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