Product name:

Product model: IS200STAIH1A

Quantity: inventory

Part No./PN: IS200STAIH1A

Warranty: We provide warranty service for IS200STAIH1A

Shipping Port:FuJian

Product technical documents: no relevant documents

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GE General Electric Technical Specifications: IS200STAIH1A

The IS200STAIH1A MDX-BRAM is one of Mostek’s complete line of STD

Bus-compatible laO microcomputer modules. The MDX

BRAM is desig ned to save up to 4K bytes of memory duri ng

a power fa i lure. Power degradation is detected by either the

resident 5 volt monitoring circuitry or an external powerfail

detect module (MDX-PFD). When a power IS200STAIH1A failure is

detected, the on-board battery power is enabled to retain

memory data.

The MDX-BRAM provides 4K bytes of random access

memory (RAM). The addressing of the board is jumper

selectable on 4K boundaries within a 64K address space.

The MDX-BRAM2 provides 2K bytes of RAM.


brand Product Name Product model Order No
GE Fanuc Module card IS200STAIH1A nothing
Place of Origin Marketable land Imported or not defects liability period
Europe and America Nationwide and overseas yes a year
Place of shipment Delivery method How to use Applicable industries
Xiamen Shunfeng Express Commissioning and installation Power Plant Steel Plant Cement Plant Shipboard Papermaking
Service advantages Foreign import, goods preparation and supply Reasonable price and reliable quality Pictures are for reference only
Product features Primary source of goods, supply by model After sales guarantee Chen 1810693-7731


The IS200STAIH1A  board has a DC power monitor circuit to detect when

the 5 volt supply line is lower than a specified value. It also

contains the interface circuitry to monitor an external signal

(lSYSRESET) indicating a power failure has been detected

by the MDX-PFD module. When a power failure is detected

by either method, battery power is enabled and all access to

the board is blocked until primary power is restored.

Battery power is supplied by three NiCad cells which can

provide enough energy to retain memory data for up to five

days. An on-board battery charging circuit is provided to

ensure the batteries are kept fully charged while the board

is in use. Duration of data retention may be considerably

less when the batteries are not fully charged. An MDX

BRAM Block Diagram is shown in Figure 2.

Address Decoder and Buffer

All the address lines are buffered. The first ten (AO-A9) go

directly from the buffer to the array, and the other six

(A 1 a-A 15) go through a compare circuit for the board

address and a decode circuit to form the four chip select


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Lead time problem
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livery can be arranged on the same day after the contract payment is signed
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