GE IS200MVRPH1A PC board power distribution

Product name:
GE IS200MVRPH1A PC board power distribution

Product model: IS200MVRPH1A

Quantity: inventory

Part No./PN: IS200MVRPH1A

Warranty: We provide warranty service for IS200MVRPH1A

Shipping Port:FuJian

Product technical documents: no relevant documents

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GE General Electric Technical Specifications: IS200MVRPH1A

The memory IS200MVRPH1A map PROM (U14) contains eight memory

configuration maps. As the chart in Figure 8 indicates,

resolution of the maps is 2K blocks. The numbers enclosed

in brackets [ ], represent BYTEWYDE IS200MVRPH1A memory sockets on

board as shown in Figure 5. The memory installed may be

either RAM or ROM. The indication (RAM) represents off

board RAM.

If bank switching is desired, the section entitled MULTIPLE

MEMORY BANK OPERATION describes the use of jumper

J4 and the various memory maps in obtaining this.


brand Product Name Product model Order No
GE Fanuc Module card IS200MVRPH1A nothing
Place of Origin Marketable land Imported or not defects liability period
Europe and America Nationwide and overseas yes a year
Place of shipment Delivery method How to use Applicable industries
Xiamen Shunfeng Express Commissioning and installation Power Plant Steel Plant Cement Plant Shipboard Papermaking
Service advantages Foreign import, goods preparation and supply Reasonable price and reliable quality Pictures are for reference only
Product features Primary source of goods, supply by model After sales guarantee Chen 1810693-7731


The IS200MVRPH1A MDX-CPU4 supports a memory bank switching

operation wi:lich aUows memory expansion beyond the

normal 64K byte limitation of the Z80.

There are two basic schemes of bank switching available.

One method requires removal of jumper J4. With J4

removed, write a select byte to port FFH as shown in Figure

  1. This sel.ects one of eight different banks and utilizes

memory maps 4,;5: and 6 (see Figure 8). This does not take

advantage of any CPU4 IS200MVRPH1A memory except the bootup PROM.

The alternative scheme .Ieaves jl,lmper J4 in position and

has the PROM in socket fbe a combination bootup PROM

and kernel. After power-up, a 07H written to port FFH

allows the user to have his kernel on CPU4 and do bank

switching via any port except FFH.


An LED is available to be programmed on/off at bit 04 (1 X)

of port FFH. This may be used as a visual selftest indicatoror

other appropriate user fU,nctions. This. bit is also used inthe

memory bank switching mode and the indicator’ will

illuminate when addressing bank 4.

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Lead time problem
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