The following sections provide additional information pertaining to the MVME5500 VME bus interface settings as configured by MOTLoad. A few VME settings are controlled by hardware jumpers, while the majority of the VME settings are managed by the firmware command utility vmeCfg.
Default VME Settings
As shipped from the factory, the firmware on the MVME5500 will program default values into the Universe II VME Interface chip. The firmware allows certain VME settings to be changed in order for the user to customize his/her environment. The following is a description of the default VME settings that are changeable by the user. For more information, refer to the MOTLoad User’s Manual and Tundra’s Universe II User Manual, listed in Appendix C, Related Documentation.
VME3PCI Master Enable = Y
N = Do not set up or enable the VMEbus Interface.
Y = Set up and enable the VMEbus Interface.
PCI Slave Image 0
This image is set to zeroes and thus disabled.
PCI Slave Image 1 Control = C0820000
Sets LSI1_CTL to indicate that this image is enabled, write posting is enabled, VMEbus data width is 32 bits, VMEbus address space is A32, data and non-supervisory AM encoding, no BLT transfers to the VMEbus, and to accept addresses in PCI memory space.
PCI Slave Image 1 Base Address Register = 91000000
Sets LSI1_BS to indicate that the lower bound of PCI memory addresses to be transferred to the VMEbus by this image is 0x91000000.
Sets LSI1_BD to indicate that the upper bound of PCI memory addresses to be transferred by this image is 0xB0000000.
PCI Slave Image 1 Translation Offset = 70000000
Sets LSI1_TO to indicate that the PCI memory address is to be translated by 0x70000000 before presentation on the VMEbus; the result of the translation is: 0x91000000 + 0x70000000 = 0x101000000, thus 0x01000000 on the VMEbus.
PCI Slave Image 2 Control = C0410000
Sets LSI2_CTL to indicate that this image is enabled, write posting is enabled, VMEbus data width is 16 bits, VMEbus address space is A24, data and non-supervisory AM encoding, no BLT transfers to the VMEbus, and to accept addresses in PCI memory space.
PCI Slave Image 2 Base Address Register = B0000000
Sets LSI2_BS to indicate that the lower bound of PCI memory addresses to be transferred to the VMEbus by this image is 0xB0000000.
Sets LSI2_BD to indicate that the upper bound of PCI memory addresses to be transferred by this image is 0xB1000000.
PCI Slave Image 2 Translation Offset = 40000000
Sets LSI2_TO to indicate that the PCI memory address is to be translated by 0x40000000 before presentation on the VMEbus; the result of the translation is: 0xB0000000 + 0x40000000 = 0xF0000000, thus 0xF0000000 on the VMEbus.
PCI Slave Image 3 Control = C0400000
Sets LSI3_CTL to indicate that this image is enabled, write posting is enabled, VMEbus data width is 16 bits, VMEbus address space is A16, data and non-supervisory AM encoding, no BLT transfers to the VMEbus, and to accept addresses in PCI memory space.
PCI Slave Image 3 Base Address Register = B3FF0000
Sets LSI3_BS to indicate that the lower bound of PCI memory addresses to be transferred to the VMEbus by this image is 0xB3FF0000.
Sets LSI3_BD to indicate that the upper bound of PCI memory addresses to be transferred by this image is 0xB4000000.
PCI Slave Image 3 Translation Offset = 4C000000
Sets LSI3_TO to indicate that the PCI memory address is to be translated by 0x4C000000 before presentation on the VMEbus; the result of the translation is: 0xB3FF0000 + 0x4C000000 = 0xFFFF0000, thus 0xFFFF0000 on the VMEbus.
PCI Slave Image 4-7
These images are set to zeroes and thus disabled.
VMEbus Slave Image 0 Control = E0F20000
Sets VSI0_CTL to indicate that this image is enabled, write and read posting is enabled, program/data and supervisory AM coding, data width is 32 bits, VMEbus A32 address space, 64-bit PCI transfers are disabled, PCI Lock on RMW cycles are disabled, and to transfer into PCI memory space.
VMEbus Slave Image 0 Base Address Register = 00000000
Sets VSI0_BS to define the lower bound of VME addresses to be transferred to the local PCI bus is 0x00000000.
Sets VSI0_TO to define that no translation of the VMEbus address is to occur when transferred to the local PCI bus. According to the CHRP map in use by MOTLoad, this will result in transfers to local DRAM; that is, 0x00000000 on the VMEbus is 0x00000000 in local DRAM.
VMEbus Slave Image 1-7
These images are set to zeroes and thus disabled.
VMEbus Register Access Image Control Register = 00000000
The VRAI_CTL register is disabled.
VMEbus Register Access Image Base Address Register = 00000000
The contents of the VRAI_BS register are not applicable since the image is disabled.
PCI Miscellaneous Register = 10000000
The LMISC register is set for Universe I compatibility and the coupled window timer is disabled.
Special PCI Slave Image Register = 00000000
The SLSI register is disabled.
Master Control Register = 00C00000
The MAST_CTL register is set to retry forever before the PCI master signals error, transfer 128 bytes on posted writes before release, use VMEbus request level 3, request mode = Demand, Release When Done, align PCI transfers on 32 bytes and use PCI bus 0.
Miscellaneous Control Register = 52040000
Sets MISC_CTL register to utilize 256 second VMEbus timeout, round robin arbitration, 256 second arbitration timeout, do not use BI-mode and assertion of VIRQ1 is to be ignored.
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Sets LSI3_BD to indicate that the upper bound of PCI memory addresses to be transferred by this image is 0xB4000000.
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