Name: MVME5100-0163 Motorola Emerson plc
Price: 5431 CNY
Availability: InStock

Description

The MVME5100-0163 Single Board Computer Programmer’s Reference Guide provides the information you will need to program your MVME5100-0163 Single Board Computer. The MVME5100 is a high-performance VME single board computer featuring the Motorola Computer Group (MCG) PowerPlus II architecture with a choice of PowerPC® processors—either Motorola’s MPC7400 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750.
Introduction
The MVME5100-0163 is a state-of-the-art Single Board Computer. It incorporates Motorola’s PowerPlus II architecture with a choice of PowerPC processors—either Motorola’s MPC7400 with AltiVec™ technology for algorithmic intensive computations or the low-power MPC750. The MVME5100-0163 incorporates a highly optimized PCI interface and memory controller enabling up to 582MB memory read bandwidth and 640 MB burst write bandwidth. The on-board Hawk ASIC provides the bridge function between the processor’s bus and the PCI bus. It provides 32-bit addressing and 64-bit data; however, 64-bit addressing (dual address cycle) is not supported. The ASIC also supports various processor external bus frequencies up to 10MHz.
Processor PLL Configuration
The processor internal clock frequency (core frequency) is a multiple of the system bus frequency. The processor has four configuration pins, PLL_CFG[0:3], for hardware strapping of the processor core frequency between 2x and 8x the system bus frequency, in 0.5x steps. The PLL configuration shall be dynamic at power-up and be dependent upon the existence of a memory mezzanine attached to the host board.
The MVME5100-0163 incorporates an L2 cache using a 2-way, set-associative tag memory located in the MPC7400 processor, with external directmapped synchronous SRAMs for data storage. The external SRAMs are accessed through a dedicated L2 cache port on the processor.
System Memory
MVME5100-0163 system memory characteristics are fully compatible with those of the Hawk ASIC for memory Blocks A, B, C, and E. The on-board memory Blocks are Blocks A and B. The optional add-on mezzanine memory Blocks are C (first mezzanine attached) and E (second mezzanine attached).

The MVME5100-0163 SPD uses the SPD JEDEC standard definition. On board SPD for SDRAM Bank A or both A and B of the Hawk shall be accessed at Address $A8 . Only Bank A or Banks A and B will be populated. If both banks A and B are populated, they will be the same speed and memory size. Memory Mezzanine 1 SPD for SDRAM Bank C of the Hawk shall be accessed at Address $AA. Memory Mezzanine 2 SPD for SDRAM Bank E of the Hawk shall be accessed at address $AC.

MVME5100-0163 PDF

MVME5101

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