Name: MVME2604 MOTOROLA I/O VME Processor Module
Price: 3232 CNY
Availability: InStock

Description

1. System Block Diagram

The MVME2604 series offers an optional 256KB look-aside external cache.
The Falcon chipset controls the boot Flash memory and ECC DRAM.
The Raven ASIC serves two key roles: a 64-bit PCI host bridge and an MPIC (Multiprocessor Interrupt Controller).
PCI Bus Devices: SCSI controller, VME interface, Ethernet controller, and one PMC slot.
ISA Bus Devices:
- A Super I/O device that provides standard I/O functions.
- NVRAM (Non-Volatile RAM)/RTC (Real-Time Clock).
- Optional synchronous serial ports.

2. Overview

2.1 Core Hardware Configuration

The MVME2604 series is a family of single-slot SBCs (Single-Board Computers) with the following core components:

MPC603/604 processor
Raven PCI Bridge & Interrupt Controller
Falcon chipset (ECC Memory Controller)
5MB or 9MB of Flash memory
16MB to 256MB of ECC-protected DRAM
A comprehensive set of I/O peripheral features

2.2 I/O Peripheral Distribution

PCI Bus Peripherals:
- SCSI chip
- Ethernet chip
- Universe VMEbus interface ASIC
- One PMC slot
ISA Bus Peripherals:
- P1284/Parallel port
- Two asynchronous serial ports
- Two sync/async serial ports
- Real-time clock (RTC)
- Counters/timers

2.3 VMEbus Connection & Power Supply

The MVME2604 series board interfaces with the VMEbus via P1 and P2 connectors. These connectors adopt the new 5-row, 160-pin design specified in the proposed VME64 Extension Standard.
Power is drawn from the VMEbus backplane through P1 and P2 connectors, including +5V, +12V, and -12V. The 3.3V power supply is regulated onboard from the +5V input.

2.4 Front Panel Connectors

The front panel of the MVME2604 series board includes three key connectors:

A 6-pin circular DIN connector for the keyboard interface
A 6-pin circular DIN connector for the mouse interface
A 50-pin connector for the floppy drive and status LEDs

3. Key Configuration Notes

Programmable via the Falcon chipset.
To enable the “Processor-hole” area:
- Program the Falcon chipset to ignore the address range 0x000A0000 – 0x000BFFFF.
- Program the Raven ASIC to map this address range to PCI memory space.
Programmable via the Raven ASIC.
CHRP (Common Hardware Reference Platform) requires the starting address of the PCI memory space to be 256MB-aligned.
Programmable via the Raven ASIC to operate in either contiguous or spread-I/O mode.
The actual size of each ROM/FLASH bank may vary.
After a reset:
- If the rom_b_rv control bit is cleared, the first 1MB of ROM/FLASH Bank A is mapped to this address range.
- If the rom_b_rv control bit is set, this address range maps to ROM/FLASH Bank B.
This address range can be mapped to the VMEbus by programming the Universe ASIC accordingly. The map shown is the recommended setting, which uses the Special PCI Slave Image and two of the four programmable PCI Slave Images.
The only way to generate a PCI Interrupt Acknowledge cycle (8259 IACK) is to perform a read access to the Raven’s PIACK register at address 0xFEFF0030.

MVME2604 PDF
MVME2604

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