15 programmable levels for Interrupt & Processor Task priority
Provision for connecting an external 8259 for ISA/AT compatibility
Distributed interrupt delivery for external I/O interrupts
Direct/Multicast interrupt delivery for interprocessor and timer interrupts
Four Interprocessor Interrupt (IPI) sources
Four built-in timers
Processor initialization control functionality
2. Architecture Overview
The Raven PCI Slave integrates two address decoders to map RavenMPIC registers into either PCI IO space or PCI Memory space. Access to these registers requires both MPC and PCI bus mastership, and includes operations such as interrupt initialization, timer initialization, and interrupt vector reads.
The RavenMPIC accepts interrupt inputs from six categories of sources:
16 external interrupt sources
4 interprocessor interrupt sources
4 timer interrupt sources
1 Raven internal error detection source
Interrupt Activation Modes
External interrupts 1–15: Support two activation modes — low level or active-high positive edge.
External interrupt 0: Flexible activation (level or edge) with configurable polarity.
Interprocessor and timer interrupts: Triggered by event activation.
3. CSR Readability Rules
Unless explicitly stated otherwise, all registers are readable and return the last written value. Exceptions follow these rules:
IPI dispatch registers and EOI registers: Return 0 when read.
Interrupt source ACT bit: Returns the current status of the interrupt source.
Interrupt acknowledge register: Returns the vector of the highest-priority pending interrupt; it is also the only register with read side-effects.
Reserved bits: Return 0 when read.
4. Interrupt Priority Mechanisms
4.1 Interrupt Source Priority
Each interrupt source is assigned a priority value ranging from 0 (lowest) to 15 (highest).
An interrupt can only be delivered to a processor if the source’s priority is higher than the destination processor’s current task priority.
Setting a source’s priority to 0 disables that interrupt (inhibits delivery).
4.2 Processor’s Current Task Priority
Each processor has a task priority register, configured by system software to reflect the importance of the task running on the processor.
A processor will not receive interrupts with a priority level that is equal to or lower than its current task priority.
Setting the current task priority to 15 blocks all interrupts from being delivered to that processor.
5. Interrupt Nesting Rules
A processor will never have an in-service interrupt preempted by an interrupt of equal or lower priority. The lifecycle of an in-service interrupt is defined as:
Starts when the interrupt’s vector is returned during an interrupt acknowledge cycle.
Ends when an EOI (End of Interrupt) signal is received for that interrupt.
The EOI cycle specifically marks the completion of processing for the highest-priority in-service interrupt.
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