Name: MVME133-2 CPU BOARDS NEW
Price: 4222 CNY
Availability: InStock

Description

When the MPU initiates an interrupt acknowledge cycle, the interrupt handler determines the acknowledge level by examining [A01] – [A03]. It then decides which device the cycle is for. Finally, it activates [AVEC*] to indicate to the MPU to generate the interrupt vector internally if the acknowledge cycle was for VMEbus ACFAIL*, ABORT switch, or the real-time clock. If the acknowledge cycle is for the Z8530, the MC68901 MFP, or the VMEbus, then it indicates a vector fetch cycle to the appropriate device. If both onboard and VMEbus interrupts are activated on the acknowledge level, the interrupt handler acknowledges the onboard The MVME133 provides no protection against inadvertent writes to EEPROM that might happen during power on/off transitions. Most devices provide some level of internal protection. In order to gain “absolute protection”, devices with additional “software protection” are recommended.seven and have the same interrupt offset vector. Therefore, the software handler routine for this autovector must interrogate the [ACFAIL] bit in the MSR to determine the actual interrupt source.

The MVME133 has four 28-pin ROM/PROM/EPROM/ EEPROM sockets that are organized as two banks with two sockets per bank. Each bank appears as a 16-bit word port to the MPU and can be separately configured for 8K x 8, 16K x 8, 32K x 8, or 64K x 8 ROM/PROM/EPROMs; or for 2K x 8, 8K x 8, or 32K x 8 EEPROMs. When a bank is configured for EEPROM, writes to that bank must always be 16-bit wide. There are several different algorithms for erasing/writing to EEPROMS, depending on the manufacturer. The MVME133 supports only those devices which have a “static RAM” compatible erase/write mechanism. The MVME133 connects pin 1 of both devices in bank 1 to the DCDA input of the Z8530, and pin 1 of both devices in bank 2 to the CTSA input of the 28530. DCDA and CTSA can be used as general purpose status inputs for monitoring those devices which provide RDY/BSY* status on pin 1. Note that the MVME133 requires that the EEPROMs must allow wired-OR on the RDY/BSY* pin.
The MVME133 uses the Z8530 to implement its two multiprotocol serial ports. Port A of the 28530 is connected to RS-485 drivers and receivers. Port B of the Z8530 is connected to RS-232C drivers and receivers. Because of its internal structure, there are several means of obtaining the baud rate clocks for each of the two serial channels. Each channel within the Z8530 has a programmable baud rate generator. The baud rate generator input can be from the RTXC input or from PCLK. The hardware on the MVME133 allows the RTXC pin for each channel to be connected to an external source or to the onboard 1.23 MHz clock. Table 4-5 shows the values in the Z8530 channel time constant register that are required to create some common baud rates.

MVME133-2 CPU BOARDS

MVME133-2 PDF
MVME133-2

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