GE VMIVME-4132-000 Analog output board

Description

Model: VMIVME-4132-000，Due to the large number of goods, only some goods have been uploaded. If you can’t find the goods you want, please consult the seller, and we will serve you wholeheartedly.

Analog inputs from connectors P3 and P4 are routed through low pass Input

Filters and OP AMP Buffers to the input multiplexers shown in Figure 3.6.1-1.

VMIVME-4132-000 Channels 00 to 31 are connected through P4 and Channels 32 to 63 are connected

through P3. To provide at least one ground in each of the input connectors, the LOW

inputs for Channels 31 and 63 can be jumpered individually to AGND, or can be left

VMIVME-4132-000 ungrounded (see Sections 5.4 and 5.6). AGND is the internal analog ground. The

center row (B row) pins on P3 and P4 are connected to AGND. This provides a return

for all channels if 96-wire ribbon cables are used for the analog inputs.

The Analog Multiplexers route one of each group of eight channels to the

VMIVME-4132-000 PGA multiplexers, which in turn selects an input to route to the PGA. Input address

lines A0 and A1 control the input multiplexer, while A3, A4, and A5 select the PGA

multiplexer input. Each input multiplexer has an individual enable signal which

enables the multiplexer with the desired channel.

Crosstalk and source impedance errors are minimized by the input OP AMP

Buffers. The buffers provide a constant low impedance to the multiplexer inputs. Each

channel contains a buffer on each input line.

3.6.2 Gain Control

The Programmable Gain Amplifier (PGA) applies a gain of x1 or x10 to the

differential channel from the PGA multiplexer, and produces a single-ended output.

PGA gain is selected by the GAIN_X1_L control line (Section 3.2).

3.6.3 VMIVME-4132-000 Analog-to-Digital Conversion

The output of the PGA is buffered by a unity gain buffer and digitized by the

16-bit successive approximation A/D Converter shown in Figure 3.6.3-1a. The ADC

has a built-in sample and hold. Each conversion is initiated by the sample command,

and the read ADC strobe writes the digitized value to the data buffer through the

internal data bus. Total conversion time is 10 µsec at the highest sample rate

available. The sample command takes 2 µsec, leaving 8 µsec for actual A/D

conversion. The ADC timing is shown in Figure 3.6.3-1b.

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